4DIR1401H datasheet(13/60 Pages) INFINEON

13 / 60 page

3.2

Timing diagrams

VINX

VOUTX

VDDI

VDDO

Figure 11

Test circuit

Figure 12 illustrates the input-to-output propagation delays as observed at the capacitively loaded output.

INX

OUTX

tPDon

50%

tPDoff

50%

VDDI

Figure 12

Propagation delays

Figure 13 illustrates the rise and fall time as observed at the capacitively loaded output.

10%

90%

trise

tfall

INX

OUTX

Figure 13

Rise, fall times

Figure 14 illustrates the output behavior to supply UVLO events when VDD1/2 crosses the UVLO thresholds during

rising or falling transitions (power-up, power-down, supply noise). Note that the input (VDD1) and output (VDD2)

supplies are rising and falling at the same time.

UVLOon

UVLOoff

DATA

VDD1/2 – GND1/2

OUTX – GND1/2

Z means ‘high-impedance

D means default o/p state. Refer to product variants

Figure 14

Under-voltage lockout

Figure 15 illustrates the propagation delay between the rising and falling edges of the EN signal to the output

following the input signal.

ISOFACE™ Digital Isolator 4DIRx4xxH family

Robust Digital Isolators with precise timing and low power consumption

3 Functional description

Datasheet

V1.6

2024-04-17

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