Application information

TSA1204

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Figure 27.

Figure 27 shows a DC-coupled configuration with forced VREFP and INCM to the 1 V DC

analog input while VREFM is connected to ground; the differential amplitude obtained is

8.4

Clock input

The quality of your TSA1204 converter is very dependent on your clock input accuracy, in

terms of aperture jitter; the use of a low jitter crystal controlled oscillator is recommended.

Further points to consider in your implementation are:

●

The duty cycle must be between 45% and 55%.

●

The clock power supplies must be independent from the ADC output supplies to avoid

digital noise modulation on the output.

●

When powered-on, the circuit needs several clock periods to reach its normal operating

conditions. Therefore, it is recommended to keep the circuit clocked to avoid random

states before applying the supply voltages.

8.5

Power consumption optimization

The internal architecture of the TSA1204 makes it possible to optimize power consumption

according to the sampling frequency of the application. For this purpose, an external resistor

optimized over the full sampling range (0.5 Msps up to 20 Msps).

The TSA1204 combines the highest performance and the lowest consumption at 20 Msps

environment.

In the lower sampling frequency range, this value of resistor may be adjusted in order to

decrease the analog current without any degradation of the dynamic performance.

Table 12 gives some values to illustrate this.

TSA1204

VIN

VINB

INCM

330pF

4.7

μF

10nF

analog

DC

AC+DC

VREFP

VREFM

DC

analog

VREFP-VREFM = 1 V