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PS700 데이터시트(PDF) 27 Page - Microchip Technology |
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PS700 데이터시트(HTML) 27 Page - Microchip Technology |
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27 / 38 page ![]() 2004 Microchip Technology Inc. DS21760F-page 27 PS700 4.5 Power-on Reset When power is first applied to the VC1 input, the PS700 automatically executes a Power-on Reset sequence. The device is held in a Reset state while the voltage is below the minimum operating threshold, VPOR. When the voltage on the VC1 input rises above the VPOR threshold, the PS700 will initialize itself as described below. When initialization is complete, the PS700 will enter Run mode. During the Power-on Reset sequence, the registers are loaded with initial values from EEPROM locations 0x020-0x087. These locations are reserved to contain register initialization values. In a battery pack applica- tion, a Power-on Reset typically happens only at the time of pack manufacture, when the cells are first con- nected to the battery monitoring pcb containing the PS700. Data in the EEPROM locations, (Bank 0) 0:0x020- 0:0x07F, will be loaded into the corresponding register locations in (Bank 1) 1:0x020-1:0x07F. Data in the EEPROM locations, (Bank 1) 0:0x080-0:0x084, will be loaded into the corresponding Cal/Setup register loca- tions in (Bank 2) 2:0x080-2:0x084. In all cases, EEPROM register initialization locations corre- sponding to “Reserved” register locations must contain the value of 0x00h in order to insure proper operation following a Power-on Reset. 4.6 Factory Register Initialization The EEPROM register initialization locations are pro- grammed with a set of default values at the time that the PS700 is manufactured. This programming results in the following general operational state of a PS700 following a Power-on Reset: • All accumulators and time counters disabled and reset to ‘0’ • All A/D conversion disabled • A/D registers programmed with their anticipated input source, resolution and input reference • Sample and Shelf-Sleep modes disabled • All Sample-Sleep mode entry methods disabled and trip point values zeroed • GPIO inputs on VC2 and NTC disabled • SMBus address = 0x16 • Factory calibrated trim values for band gap, voltage reference, auxiliary oscillator and main oscillator Table 4-6 lists in detail the values that are programmed into the EEPROM register initialization locations. Note: Do not overwrite the factory trimmed values. |
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