DSPIC33FJ12MC02ESS datasheet(186/284 Pages) MICROCHIP

186 / 284 page

dsPIC33FJ12MC201/202

DS70265B-page 184

Preliminary

17.11 Slope Control

The I2C standard requires slope control on the SDAx

and SCLx signals for Fast mode (400 kHz). The control

bit, DISSLW, enables the user application to disable

slew rate control if desired. It is necessary to disable

the slew rate control for 1 MHz mode.

17.12 Clock Arbitration

Clock arbitration occurs when the master deasserts the

SCLx pin (SCLx allowed to float high) during any

receive, transmit or Restart/Stop condition. When the

SCLx pin is allowed to float high, the Baud Rate

Generator (BRG) is suspended from counting until the

SCLx pin is actually sampled high. When the SCLx pin

is sampled high, the BRG is reloaded with the contents

of I2CxBRG and begins counting. This process

ensures that the SCLx high time will always be at least

one BRG rollover count in the event that the clock is

held low by an external device.

17.13 Multi-Master Communication, Bus

Collision and Bus Arbitration

Multi-Master mode support is achieved by bus

arbitration. When the master outputs address/data bits

onto the SDAx pin, arbitration takes place when the

master outputs a ‘1’ on SDAx by letting SDAx float high

while another master asserts a ‘0’. When the SCLx pin

floats high, data should be stable. If the expected data

on SDAx is a ‘1’ and the data sampled on the

SDAx pin = 0, then a bus collision has taken place. The

master sets the I2C master events interrupt flag and

resets the master portion of the I2C port to its Idle state.

17.14 Peripheral Pin Select Limitations

The I2C module has limited peripheral pin select

functionality. When the ALTI2C bit in the FPOR

configuration register is set to ‘1’, I2C module uses

SDAx/SLCx pins. When ALTI2C bit is ‘0’, I2C module

uses ASDAx/ASCLx pins.\

DSPIC33FJ12MC02ESS 데이터시트(PDF) 186 Page - Microchip Technology