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DSPIC33FJ12MC02ESS 데이터시트(PDF) 19 Page - Microchip Technology |
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DSPIC33FJ12MC02ESS 데이터시트(HTML) 19 Page - Microchip Technology |
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19 / 284 page ![]() © 2007 Microchip Technology Inc. Preliminary DS70265B-page 17 dsPIC33FJ12MC201/202 bit 1 RND: Rounding Mode Select bit 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled bit 0 IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops REGISTER 2-2: CORCON: CORE CONTROL REGISTER (CONTINUED) Note 1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. |
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