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DSPIC33FJ12MC02ESS 데이터시트(PDF) 197 Page - Microchip Technology |
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DSPIC33FJ12MC02ESS 데이터시트(HTML) 197 Page - Microchip Technology |
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197 / 284 page ![]() © 2007 Microchip Technology Inc. Preliminary DS70265B-page 195 dsPIC33FJ12MC201/202 bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). |
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