1998 Dec 16

31

Philips Semiconductors

Preliminary specification

TDA9321H

Notes to the characteristics

to avoid too big differences between them.

2. On set AGC.

3. This parameter is not tested during production and is just given as application information for the designer of the

television receiver.

5. The optimum temperature stability of the PLL can be obtained when a TOKO coil as given in Table 55 is applied.

6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix

batches which are made in the pilot production period.

7. Measured at 10 mV (RMS value) top sync input signal.

8. So called projected zero point, i.e. with switched demodulator.

9. Measured in accordance with the test line given in Fig.5. For the differential phase test the peak white setting is

reduced to 87%.

The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and

smallest value relative to the subcarrier amplitude at blanking level.

The differential phase is defined as the difference in degrees between the largest and smallest phase angle.

10. This figure is valid for the complete video signal amplitude (peak white-to-black). See Fig.6.

11. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal).

delay between mid sync of input

and start of clamping pulse

note 30

3.0

3.2

3.4

µs

input voltage range

0

−

5.5

V

LOW-level input voltage

−−

1.5

V

HIGH-level input voltage

3.5

−−

V

LOW-level input current

−−

−10

µA

HIGH-level input current

−−

10

µA

LOW-level output voltage on

pin SDA

−−

0.4

V

HIGH-level output voltage

4.0

5.0

5.5

V

LOW-level output voltage

−

0.2

0.4

V

output sink current

2

−−

mA

output source current

2

−−

mA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT