PIC18F44J10-ESLASHML datasheet(252/358 Pages) MICROCHIP

252 / 358 page

PIC18F45J10 FAMILY

DS39682C-page 250

Preliminary

BCF

Bit Clear f

Syntax:

BCF

f, b {,a}

Operands:

≤ f ≤ 255

≤ b ≤ 7

∈ [0,1]

Operation:

→ f<b>

Status Affected:

None

Encoding:

1001

bbba

ffff

Description:

Bit ‘b’ in register ‘f’ is cleared.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write

Example:

BCF

FLAG_REG,

7, 0

Before Instruction

FLAG_REG =

C7h

After Instruction

FLAG_REG =

47h

Branch if Negative

Syntax:

Operands:

-128

≤ n ≤ 127

Operation:

if Negative bit is ‘1’

(PC) + 2 + 2n

→ PC

Status Affected:

None

Encoding:

1110

0110

nnnn

Description:

If the Negative bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Decode

Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

‘n’

Process

Data

operation

Example:

HERE

Jump

Before Instruction

address (HERE)

After Instruction

If Negative

address (Jump)

If Negative

address (HERE + 2)

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