| 전자부품 데이터시트 검색엔진 |
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PIC18F44J10-E/ML 데이터시트(PDF) 316 Page - Microchip Technology |
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PIC18F44J10-E/ML 데이터시트(HTML) 316 Page - Microchip Technology |
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316 / 358 page ![]() PIC18F45J10 FAMILY DS39682C-page 314 Preliminary © 2007 Microchip Technology Inc. FIGURE 23-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING FIGURE 23-7: BROWN-OUT RESET TIMING TABLE 23-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. No. Symbol Characteristic Min Typ Max Units Conditions 30 TMCLMCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period (no postscaler) 2.8 4.1 5.4 ms 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period 33 TPWRT Power-up Timer Period 46.2 66 85.8 ms 34 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset —2 — μs 38 TCSD CPU Start-up Time — 200 — μs VDD MCLR Internal POR PWRT Time-out Oscillator Time-out Internal Reset Watchdog Timer Reset 33 32 30 31 34 I/O pins 34 Note: Refer to Figure 23-3 for load conditions. VDD BVDD VBGAP = 1.2V VIRVST Enable Internal Internal Reference Reference Voltage Voltage Stable |
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