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PIC18F4685-I/SP 데이터시트(PDF) 342 Page - Microchip Technology |
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PIC18F4685-I/SP 데이터시트(HTML) 342 Page - Microchip Technology |
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342 / 484 page ![]() PIC18F2682/2685/4682/4685 DS39761B-page 340 Preliminary © 2007 Microchip Technology Inc. FIGURE 23-8: ERROR MODES STATE DIAGRAM 23.15 CAN Interrupts The module has several sources of interrupts. Each of these interrupts can be individually enabled or disabled. The PIR3 register contains interrupt flags. The PIE3 register contains the enables for the 8 main interrupts. A special set of read-only bits in the CANSTAT register, the ICODE bits, can be used in combination with a jump table for efficient handling of interrupts. All interrupts have one source, with the exception of the error interrupt and buffer interrupts in Mode 1 and 2. Any of the error interrupt sources can set the error interrupt flag. The source of the error interrupt can be determined by reading the Communication Status register, COMSTAT. In Mode 1 and 2, there are two interrupt enable/disable and flag bits – one for all transmit buffers and the other for all receive buffers. The interrupts can be broken up into two categories: receive and transmit interrupts. The receive related interrupts are: • Receive Interrupts • Wake-up Interrupt • Receiver Overrun Interrupt • Receiver Warning Interrupt • Receiver Error-Passive Interrupt The transmit related interrupts are: • Transmit Interrupts • Transmitter Warning Interrupt • Transmitter Error-Passive Interrupt • Bus-Off Interrupt Bus- Off Error- Active Error- Passive RXERRCNT < 127 or TXERRCNT < 127 RXERRCNT > 127 or TXERRCNT > 127 TXERRCNT > 255 128 occurrences of 11 consecutive “recessive” bits Reset |
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