PIC18F258-ESLASHLSQTP datasheet(203/402 Pages) MICROCHIP

203 / 402 page

DS41159E-page 201

PIC18FXX8

19.2

CAN Module Registers

There are many control and data registers associated

with

the

CAN

module.

For

convenience,

their

descriptions have been grouped into the following

sections:

• Control and Status Registers

• Transmit Buffer Registers (Data and Control)

• Receive Buffer Registers (Data and Control)

• Baud Rate Control Registers

• I/O Control Register

• Interrupt Status and Control Registers

19.2.1

CAN CONTROL AND STATUS

REGISTERS

The registers described in this section control the

overall operation of the CAN module and show its

operational status.

CANCON: CAN CONTROL REGISTER

Note:

Not all CAN registers are available in the

Access Bank.

R/W-1

R/W-0

U-0

REQOP2

REQOP1

REQOP0

ABAT

WIN2

WIN1

WIN0

—

bit 7

bit 0

bit 7-5

REQOP2:REQOP0: Request CAN Operation Mode bits

1xx

= Request Configuration mode

011

= Request Listen Only mode

010

= Request Loopback mode

001

= Request Disable mode

000

= Request Normal mode

bit 4

ABAT: Abort All Pending Transmissions bit

= Abort all pending transmissions (in all transmit buffers)

= Transmissions proceeding as normal

bit 3-1

WIN2:WIN0: Window Address bits

This selects which of the CAN buffers to switch into the Access Bank area. This allows access

to the buffer registers from any data memory bank. After a frame has caused an interrupt, the

ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer. See

Example 19-1 for code example.

111

= Receive Buffer 0

110

= Receive Buffer 0

101

= Receive Buffer 1

100

= Transmit Buffer 0

011

= Transmit Buffer 1

010

= Transmit Buffer 2

001

= Receive Buffer 0

000

= Receive Buffer 0

bit 0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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