PIC18F258-ESLASHLSQTP datasheet(68/402 Pages) MICROCHIP

68 / 402 page

PIC18FXX8

DS41159E-page 66

FIGURE 6-2:

TABLE WRITE OPERATION

6.2

Control Registers

Several control registers are used in conjunction with

the TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

6.2.1

EECON1 AND EECON2 REGISTERS

EECON1 is the control register for memory accesses.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the memory write and erase sequences.

Control bit EEPGD determines if the access will be a

program or data EEPROM memory access. When

clear, any subsequent operations will operate on the

data EEPROM memory. When set, any subsequent

operations will operate on the program memory.

Control bit CFGS determines if the access will be to the

Configuration/Calibration

registers

program

memory/data

EEPROM

memory.

When

set,

subsequent operations will operate on Configuration

registers regardless of EEPGD (see Section 24.0

“Special Features of the CPU”). When clear, memory

selection access is determined by EEPGD.

The FREE bit, when set, will allow a program memory

erase operation. When the FREE bit is set, the erase

operation is initiated on the next WR command. When

FREE is clear, only writes are enabled.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset or a WDT Time-out Reset during normal opera-

tion. In these situations, the user can check the

WRERR bit and rewrite the location. It is necessary to

reload the data and address registers (EEDATA and

EEADR) due to Reset values of zero.

Control bits, RD and WR, initiate read and write opera-

tions, respectively. These bits cannot be cleared, only

set, in software. They are cleared in hardware at the

completion of the read or write operation. The inability

to clear the WR bit in software prevents the accidental

or premature termination of a write operation. The RD

bit cannot be set when accessing program memory

(EEPGD = 1).

Table Pointer(1)

Table Latch (8-bit)

TBLPTRH

TBLPTRL

TABLAT

Program Memory

(TBLPTR)

TBLPTRU

Instruction: TBLWT*

Note

1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>.

The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash

Program Memory”.

Holding Registers

Program Memory

Note:

Interrupt flag bit, EEIF in the PIR2 register,

is set when write is complete. It must be

cleared in software.

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