PACE1757M datasheet(5/34 Pages) PYRAMID

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PACE 1757 M/ME

Page 5 of 34

Document # MICRO-10 REV B

TIMING GENERATOR STATE DIAGRAMS

Two separate and almost independent state diagrams

may be used to describe the PACE1757M machine

cycle.

The Execution Unit performs according to a cycle of

three state represented by Diagram A (the A machine)

and the External Bus Unit follows a minimum cycle of

four states, indicated in Diagram B (the B machine).

Referring to Diagram A, the paths are defined as

follows for the Execution Unit:

(0) External Reset true

(1) External Reset false

(2) ALU wait or Bus wait.

(3) ALU Branch false

(4) ALU Branch true

Diagram A

Diagram B

Diagram B defines the paths for the External Bus as

follows:

(0) External Reset false

(8) Bus Req. false

(9) Bus Req. true and Bus Av. true

(10) Bus Req. true and Bus Av. false

(11) Bus Av. false

(12) Bus Av. true

(13) RDYA false

(14) RDYA true

(16) RDYD false

(17) RDYD true and Bus Req. true and Bus Av. true

(18) RDYD true and Bus Req. false

(19) RDYD true and Bus Req. true and Bus Av. false

(20) Bus Req. true and Bus Av. true

NOTE:

Bus AV = Bus grant and Bus not busy and Bus not locked.

PACE1757M 데이터시트(PDF) 5 Page - Pyramid Semiconductor Corporation