PACE1757M datasheet(24/34 Pages) PYRAMID

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PACE 1757 M/ME

Page 24 of 34

Document # MICRO-10 REV B

SIGNAL DESCRIPTIONS (Continued)

BUS ARBITRATION

Mnemonic

Name

Description

BUS REQ

Bus request

An active LOW output that indicates the CPU requires the bus. It

becomes inactive when the CPU has acquired the bus and started the

bus cycle.

BUS GNT

Bus grant

An active LOW input from an external arbiter that indicates the CPU

currently has the highest priority bus request. If the bus is not used and

not locked, the CPU may begin a bus cycle, commencing with the next

CPU clock. A HIGH level will hold the CPU in Hi-Z state (Bz), three-

stating the IB bus status lines (D/

I, R/W, M/IO), strobes (STRBA,

STRBD), and all the other lines that go three-state when this CPU does

not have the bus.

BUS BUSY

Bus busy

An active LOW, bidirectional signal used to establish the beginning and

end of a bus cycle. The trailing edge (LOW-to-HIGH transition) is used

for sampling bits into the fault register. It is three-state in bus cycles not

assigned to this CPU. However, the CPU monitors the

BUS BUSY line

for latching non-CPU bus cycle faults into the fault register.

BUS LOCK

Bus lock

An active low, bi-directional signal used to lock the bus for successive

bus cycles. During non-locked bus cycles, the

BUS LOCK signal mimics

the

BUS BUSY signal. It is three-state during bus cycles not assigned to

the CPU. The following instructions will lock the bus: INCM, DECM, SB,

RB, TSB, SRM, STUB and STLB.

BUS GNT0 -

Bus Grant

Active-LOW outputs from the PIC indicating which master was granted

BUS GNT3

the BUS. It remains active during

BUS LOCK unless a higher master

request occurs, which resets it. However, the higher master will be

granted the BUS only after the current master's

BUS LOCK releases the

BUS.

BUS REQ0 -

Bus Request

Active-LOW inputs to the PIC that indicate a requirement for the BUS

BUS REQ3

from the 4 masters on the bus. The master assigned to pin

BUS REQ0

has the highest priority. The master assigned to pin

BUS REQ3 has the

lowest priority.

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