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CS5101A 데이터시트(PDF) 11 Page - Cirrus Logic

부품명 CS5101A
상세설명  16-bit, 100 kSps / 20 kSps A/D Converters
PDF  39 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5101A 데이터시트(HTML) 11 Page - Cirrus Logic

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CS5101A CS5102A
DS45F6
11
SWITCHING CHARACTERISTICS, ALL DEVICES
(TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF).
Notes: 28. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then SDATA is
valid tdss time after the next falling SCLK.
Parameter
Symbol
Min
Typ
Max
Unit
PDT & RBT Modes
SCLK Input Pulse Period
tsclk
200
-
-
ns
SCLK Input Pulse Width Low
tsclkl
50
-
-
ns
SCLK Input Pulse Width High
tsclkh
50
-
-
ns
SCLK Input Falling to SDATA Valid
tdss
-100
150
ns
HOLD Falling to SDATA Valid
PDT Mode
tdhs
-140
230
ns
TRK1, TRK2 Falling to SDATA Valid
(Note 28)
tdts
-65
125
ns
FRN & SSC Modes
SCLK Output Pulse Width Low
tslkl
-2tclk
-tclk
SCLK Output Pulse Width High
tslkh
-2tclk
-tclk
SDATA Valid Before Rising SCLK
tss
2tclk-100
-
-
ns
SDATA Valid After RIsing SCLK
tsh
2tclk-100
-
-
ns
SDL Falling to 1st Rising SCLK
trsclk
66tclk
2tclk
68tclk+260 ns
Last Rising SCLK to SDL Rising
CS5101A
CS5102A
trsdl
trsdl
-
-
2tclk
2tclk
2tclk+165
2tclk+200
ns
HOLD Falling to 1st Falling SCLK
CS5101A
CS5102A
thfs
thfs
6tclk
6tclk
-
-
8tclk+165
8tclk+200
ns
CH1/2 Edge to 1st Falling SCLK
tdhlri
-7tclk
64tclk
tclk



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