PM7366-PI datasheet(62/286 Pages) PMC

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

is empty and the RMAC requires a new large buffer RPDR. When reloading either of the caches,

the appropriate cache controller will read up to six new elements. The cache controller may read

fewer than six elements if there are fewer than six new elements available, or the read pointer

index is within six elements of the end of the free queue. If the read pointer is near the end of the

free queue, the cache controller reads only to the end of the queue and does not start reading

from the top of the queue until the next time a reload is required. To do so would require two host

memory transactions and would be of no benefit.

9.5

PCI Controller

The General-Purpose Peripheral Component Interconnect Controller block (GPIC) provides a 32-

bit Master and Target interface core which contains all the required control functions for Peripheral

Component Interconnect (PCI) Bus Revision 2.1 interfacing. Communications between the PCI

bus and other FREEDM-8 blocks can be made through either an internal asynchronous16-bit bus

or through one of two synchronous FIFO interfaces. One of the FIFO interfaces is dedicated to

servicing the Receive DMA Controller block (RMAC) and the other to the Transmit DMA Controller

block (TMAC).

The GPIC supports a 32-bit PCI bus operating at up to 33 MHz and bridges between the timing

domain of the DMA controllers (SYSCLK) and the timing domain of the PCI bus (PCICLK). By

itself, the GPIC does not generate any PCI bus accesses. All transactions on the bus are initiated

by another PCI bus master or by the core device. The GPIC transforms each access to and from

the PCI bus to the intended target or initiator in the core device. Except for the configuration

space registers and parity generating/checking, the GPIC performs no operations on the data.

The GPIC is made up of four sections: master state machine, a target state machine, internal

microprocessor bus interface and error/bus controller. The target and master blocks operate

independent of each other. The error/bus control block monitors the control signals from the

target and master blocks to determine the state of the PCI I/O pads. This block also generates

and/or checks parity for all data going to or coming from the PCI bus. The internal

microprocessor bus interface block contains configuration and status registers together with the

production test logic for the GPIC block.

9.5.1

Master Machine

The GPIC master machine translates requests from the RMAC and TMAC block interfaces into

PCI bus transactions. The GPIC initiates four types of PCI cycles: memory read (burst or single),

memory read multiple, memory read line and memory write (burst or single). The number of data

transfers in any cycle is controlled by the DMA controllers. The maximum burst size is determined

by the particular data path. A read cycle to the RMAC is restricted to a maximum burst size of 8

dwords and a write cycle is limited to a maximum of 32. The TMAC interface has a limit of 32

dwords on a read cycle and 8 on a write cycle.

In response to a DMA controller requesting a cycle, the GPIC must arbitrate for control of the PCI

bus. Before asserting the PCI Request line, the GPIC first does an internal arbitration to

determine the priority of service in the event that both the RMAC and TMAC are requesting

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