| 전자부품 데이터시트 검색엔진 |
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PM7366-PI 데이터시트(PDF) 101 Page - PMC-Sierra, Inc |
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PM7366-PI 데이터시트(HTML) 101 Page - PMC-Sierra, Inc |
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101 / 286 page ![]() RELEASED PM7366 FREEDM-8 DATA SHEET PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 88 Note This register is not byte addressable. Reading this register clears all the activity bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. SYSCLKA: The system clock active bit (SYSCLKA) monitors for low to high transitions on the SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is set low when this register is read. TBDA: The transmit BERT data active bit (TBDA) monitors for low to high transitions on the TBD input. TBDA is set high on a rising edge of TDB, and is set low when this register is read. |
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