PM7366-PI datasheet(120/286 Pages) PMC

120 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

107

Bit

Type

Function

Default

Bit 31 to

Bit 16

Unused

XXXXH

Bit 15

R/W

CHDIS

Bit 14

Unused

Bit 13

Unused

Bit 12

Unused

Bit 11

Unused

Bit 10

Unused

Bit 9

Unused

Bit 8

Unused

Bit 7

Unused

Bit 6

R/W

DCHAN[6]

Bit 5

R/W

DCHAN[5]

Bit 4

R/W

DCHAN[4]

Bit 3

R/W

DCHAN[3]

Bit 2

R/W

DCHAN[2]

Bit 1

R/W

DCHAN[1]

Bit 0

R/W

DCHAN[0]

This register controls the disabling of one specific channel to allow orderly provisioning of

timeslots associated with that channel.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register.

Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all

four byte enables are negated, no access is made to this register.

DCHAN[6:0]:

The disable channel number bits (DCHAN[6:0]) selects the channel to be disabled. When

CHDIS is set high, the channel specified by DCHAN[6:0] is disabled. Data in timeslots

associated with the specified channel is ignored. When CHDIS is set low, the channel

specified by DCHAN[6:0] operates normally.

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