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PM7366-PI 데이터시트(PDF) 152 Page - PMC-Sierra, Inc |
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PM7366-PI 데이터시트(HTML) 152 Page - PMC-Sierra, Inc |
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152 / 286 page ![]() RELEASED PM7366 FREEDM-8 DATA SHEET PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 139 Register 0x290 : RMAC Queue Base LSW Bit Type Function Default Bit 31 to Bit 16 Unused XXXXH Bit 15 R/W RQB[15] 0 Bit 14 R/W RQB[14] 0 Bit 13 R/W RQB[13] 0 Bit 12 R/W RQB[12] 0 Bit 11 R/W RQB[11] 0 Bit 10 R/W RQB[10] 0 Bit 9 R/W RQB[9] 0 Bit 8 R/W RQB[8] 0 Bit 7 R/W RQB[7] 0 Bit 6 R/W RQB[6] 0 Bit 5 R/W RQB[5] 0 Bit 4 R/W RQB[4] 0 Bit 3 R/W RQB[3] 0 Bit 2 R/W RQB[2] 0 Bit 1 R/W RQB[1] 0 Bit 0 R/W RQB[0] 0 This register provides the less significant word of the Receive Queue Base address. The contents of this register is held in a holding register until a write access to the companion RMAC Receive Queue Base MSW register. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. |
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