PM7366-PI datasheet(182/286 Pages) PMC

182 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

169

Bit

Type

Function

Default

Bit 31 to

Bit 16

Unused

XXXXH

Bit 15

R/W

TDRRQW[15]

Bit 14

R/W

TDRRQW[14]

Bit 13

R/W

TDRRQW[13]

Bit 12

R/W

TDRRQW[12]

Bit 11

R/W

TDRRQW[11]

Bit 10

R/W

TDRRQW[10]

Bit 9

R/W

TDRRQW[9]

Bit 8

R/W

TDRRQW[8]

Bit 7

R/W

TDRRQW[7]

Bit 6

R/W

TDRRQW[6]

Bit 5

R/W

TDRRQW[5]

Bit 4

R/W

TDRRQW[4]

Bit 3

R/W

TDRRQW[3]

Bit 2

R/W

TDRRQW[2]

Bit 1

R/W

TDRRQW[1]

Bit 0

R/W

TDRRQW[0]

This register provides the Transmit Descriptor Reference Ready Queue write address.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register.

Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all

four byte enables are negated, no access is made to this register.

TDRRQW[15:0]:

The transmit packet descriptor reference (TPDR) ready queue write bits (TDRRQW[15:0])

define bits 17 to 2 of the Transmit Packet Descriptor Reference Ready Queue write pointer.

This register is initialised by the host. The physical write address in the TDRF queue is the

sum of TDRRQW[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit

Queue Base register.

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