CSG14K_CSG8K datasheet(28/114 Pages) OSRAM

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 27

Figure 20:

SPI with 1 Master and 3 Slaves

An SPI access always consists of the transfer of the following bits (in this order), as given in

Figure 20

Figure 21:

SPI Bits Transfer Sequence

Phase

# Bits

Via

Purpose

CTRL

SPI_MOSI

Control bit indicating SPI access direction

(1 for write, 0 for read)

ADDR

SPI_MOSI

Address (0-127) of register to be accessed

DATA

N*8

SPI_MOSI

SPI_MISO

Data written to N consecutive register addresses,

starting at ADDR

Data read from N consecutive register addresses,

starting at ADDR

Via a burst mode, it is possible to write/read multiple consecutive register addresses with a

single address upload.

The state of SPI_CLK whenever SPI_CSN is high is ignored, though it is advised to stop the

clock to save unnecessary power consumption.

SPI

MASTER

SPI

SLAVE

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CSN

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CSN_1

SPI

SLAVE

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CSN

SPI

SLAVE

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CSN

SPI_CSN_2

SPI_CSN_3

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