| 전자부품 데이터시트 검색엔진 |
|
STM32F103C8T6 데이터시트(PDF) 57 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM32F103C8T6 데이터시트(HTML) 57 Page - STMicroelectronics |
|
57 / 67 page ![]() STM32F103xx Electrical characteristics 57/67 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 25 or Figure 26, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 25. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are available only on 100-pin packages. Figure 26. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF– inputs are available only on 100-pin packages. VREF+ (see note 1) STM32F103xx VDDA VSSA /VREF+ (see note 1) 1 µF // 10 nF 1 µF // 10 nF ai14388 VREF+/VDDA STM32F103xx 1 µF // 10 nF VREF–/VSSA ai14389 (See note 1) (See note 1) |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |