ST72F321AR datasheet(151/189 Pages) STMICROELECTRONICS

부품명	ST72F321AR

상세설명	64/44-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC,FIVE TIMERS, SPI, SCI, I2C INTERFACE

PDF	189 Pages

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제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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ST72321

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CLOCK CHARACTERISTICS (Cont’d)

12.5.5 Clock Security System (CSS)

Note:

1. Data based on characterization results.

12.5.6 PLL Characteristics

Note:

1. Data characterized but not tested.

The user must take the PLL jitter into account in the application (for example in serial communication or

sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several

CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the

PLL jitter.

Figure 80 shows the PLL jitter integrated on application signals in the range 125kHz to 2MHz. At frequen-

cies of less than 125KHz, the jitter is negligible.

Figure 80. Integrated PLL Jitter vs signal frequency1

Note 1: Measurement conditions: fCPU = 8MHz.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSFOSC

Safe Oscillator Frequency 1)

3MHz

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fOSC

PLL input frequency range

MHz

∆ f

CPU/ fCPU

Instantaneous PLL jitter 1)

fOSC = 4 MHz.

1.0

2.5

fOSC = 2 MHz.

2.5

4.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

4 MHz

2 MHz

1 MHz

500 kHz

250 kHz

Application Frequency

+/-Jitter (%)

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