Symbol

FBGA + PSvfBGA

Min

Max

Nom

A1 (Mounted, 0.5 Pitch)

0.180

0.280

0.230

A2 (4L Laminate)

0.260

0.340

0.300

B1 (Stacked, 0.65 Pitch), Single Die

0.270

0.330

0.300

B2 (Stacked, 0.65 Pitch), 2+0 Die

0.320

0.380

0.350

B3 (2L Laminate)

0.100

0.160

0.130

B4 (Mold Cap)

0.370

0.430

0.400

Overall Package Height

1.300

1.500

1.400

Cross Section PoP

PoP Overall Stack Up Table (mm)

PSvfBGA Top View

Cross Section PSvfBGA

A

B

C

D

E

Typical Wirecount

For Given

Package Size

Body Size

(mm)

Package Interconnect

Bottom Package

Ball Count

Nom

Die Size

(mm)

Package Interconnect

Ball Center To

Package Edge (mm)

Matrix

Ball Count

10

15

104

300

< 5.50

0.450

320

11

16

112

350

< 6.00

0.625

360

12

18

128

400

< 7.50

0.475

420

13

19

136

450

< 8.00

0.650

460

14

21

152

550

< 9.00

0.500

520

15

22

160

650

< 10.00

0.675

600

Dimensions are in line with JEDEC JC-11 standards for PoP packages in development

B - Based on 2 perimeter rows of interconnects at 0.65 mm pitch

C - Based on 4 perimeter rows of BGA balls to motherboard at 0.50 mm pitch

PSvfBGA Design Table For 0.65 mm Pitch 2 Row Stacked Interfaces

Package size

Top footprint

Bottom footprint

Max die size

A

B

C

D

Stacked Package

B4

A1

A2

B1

B2

B3

B4

A1

B3

A2

C

A

B

D

0.27 mm

E

B3

A2

B4

A1

B2

B1