ST72324BK datasheet(30/188 Pages) STMICROELECTRONICS

30 / 188 page

Supply, reset and clock management

ST72324B

30/188

Figure 14.

Reset block diagram

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In

a noisy environment, it is recommended to follow the guidelines mentioned in the electrical

characteristics section.

External power-on reset

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must

ensure by means of an external reset circuit that the reset signal is held low until VDD is over

the minimum level specified for the selected fOSC frequency.

A proper reset signal for a slow rising VDD supply can generally be provided by an external

RC network connected to the RESET pin.

Internal LVD reset

Two different reset sequences caused by the internal LVD circuitry can be distinguished:

●

Power-On reset

●

Voltage Drop reset

The device RESET pin acts as an output that is pulled low when VDD <VIT+ (rising edge) or

VDD <VIT- (falling edge) as shown in Figure 15.

The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.

Internal Watchdog reset

The reset sequence generated by a internal Watchdog counter overflow is shown in

Figure 15.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that

is pulled low during at least tw(RSTL)out.

RESET

RON

VDD

Watchdog reset

LVD reset

Internal

reset

Pulse

generator

Filter

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