HT36B2 datasheet(15/39 Pages) HOLTEK

15 / 39 page

HT36B2

Rev. 1.10

March 10, 2005

In pulse width measurement mode with the TON and TE

bits equal to one, once the TMR has received a transient

from low to high (or high to low; if the TE bit is 0) it will

start counting until the TMR returns to the original level

and resets the TON. The measured result will remain in

the register even if the activated transient occurs again.

In other words, only one cycle measurements can be

done. Until setting the TON, the cycle measurement will

function again as long as it receives further transient

pulse. Note that, in this operating mode, the timer/event

counter starts counting not according to the logic level

but according to the transient edges. In the case of

counter overflows, the counter is reloaded from the

timer/event counter and the preload register issues the

interrupt request just like the other two modes.

To enable the counting operation, the Timer ON bit

(TON; bit 4 of the TMR0C/TMR1C) should be set to 1. In

the pulse width measurement mode, the TON will be

cleared automatically after the measurement cycle is

completed. But in the other two modes the TON can only

be reset by instruction. The overflow of the timer/ event

counter is one of the wake-up sources. No matter what

the operation mode is, writing a

²0² to ET0I/ET1I can

disable the corresponding interrupt service.

In the case of timer/event counter OFF condition, writing

data to the Timer/event Counter Preload register will

also reload that data to the timer/event counter. But if

the timer/event counter is turned on, data written to the

timer/event counter will only be kept in the timer/event

counter preload register. The timer/event counter will

still operate until overflow occurs.

When the timer/event counter (reading TMR0H/TMR1H)

is read, the clock will be blocked to avoid errors. As this

may results in a counting error, this must be taken into

consideration by the programmer.

The two timer counters of the HT36B2 are internal clock

mode only, so only Timer mode can be selected. There-

fore the (TM1, TM0) bits can only be set to (TM1,TM0) =

(1,0), and the other clock modes are invalid.

Input/Output Ports

There are 32 bidirectional input/output lines labeled

from PA to PD, which are mapped to the data memory of

[12H], [14H], [16H], [18H] respectively. All these I/O

ports can be used for input and output operations. For

input operation, these ports are non-latching, that is, the

inputs must be ready at the T2 rising edge of instruction

MOV A,[m] (m=12H, 14H, 16H or 18H). For output oper-

ation, all data is latched and remains unchanged until

the output latch is rewritten.

Each I/O line has its own control register (PAC, PBC,

PCC, PDC) to control the input/output configuration.

With this control register, CMOS output or Schmitt Trig-

C K

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e I / O

R e a d I / O

S y s t e m W a k e - U p ( P A o n l y )

W e a k

P u l l - u p

P A 0 ~ P A 7

P B 0 ~ P B 7

M a s k O p t i o n

P C 0 ~ P C 7

P D 0 ~ P D 3

V D D

Input/Output Ports

S y s t e m C l o c k / 8

T M 1

T M 0

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

T i m e r / e v e n t C o u n t e r 0

P r e l o a d R e g i s t e r

T i m e r / e v e n t

C o u n t e r 0

D a t a B u s

R e l o a d

O v e r f l o w

T o I n t e r r u p t

L o w B y t e

B u f f e r

G N D

Timer/Event Counter 0/1

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