7 Detailed Description

7.1 Overview

Figure 7-1 describes the SN74ACT595, an 8-bit shift register that feeds an 8-bit D-type storage register. Both

the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks

are connected together, the shift register always is one clock pulse ahead of the storage register. Outputs QA

through QH are controlled by the output enable (OE) input. The serial output QH’ is always active.

7.2 Functional Block Diagram

RCLK

OE

SRCLR

SRCLK

SER

13

12

10

11

14

D

R

15

1

Q

A

Q

B

Q

C

Q

D

R

Q

D

Q

D

Q

2

Q

D

3

Q

E

4

Q

F

5

Q

G

6

D

R

7

9

Q

H’

Q

D

Q

Q

H

Figure 7-1. Logic Diagram (Positive Logic) for the SN74ACT595

7.3 Feature Description

7.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink

and source similar currents. The drive capability of this device may create fast edges into light loads, so routing

and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable

of driving larger currents than the device can sustain without being damaged. It is important to limit the output

power of the device to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute

Maximum Ratings must be followed at all times.

Unused push-pull CMOS outputs must be left disconnected.

7.3.2 Balanced CMOS 3-State Outputs

This device includes balanced CMOS 3-state outputs. Driving high, driving low, and high impedance are the

three states that these outputs can be in. The term balanced indicates that the device can sink and source

similar currents. The drive capability of this device may create fast edges into light loads, so routing and load

conditions should be considered to prevent ringing. Additionally, the outputs of this device can drive larger

currents than the device can sustain without being damaged. It is important for the output power of the device

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SN74ACT595

SCASE37 – NOVEMBER 2024

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