M48T35AY datasheet(7/25 Pages) STMICROELECTRONICS

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M48T35AY, M48T35AV

READ Mode

The M48T35AY/V is in the READ Mode whenever

W (WRITE Enable) is high and E (Chip Enable) is

low. The unique address specified by the 15 ad-

dress inputs defines which one of the 32,768 bytes

of data is to be accessed. Valid data will be avail-

able at the Data I/O pins within Address Access

time (tAVQV) after the last address input signal is

stable, providing that the E and G access times

are also satisfied.

If the E and G access times are not met, valid data

will be available after the latter of the Chip Enable

Access time (tELQV) or Output Enable Access time

(tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

ed before tAVQV, the data lines will be driven to an

indeterminate state until tAVQV. If the Address In-

puts are changed while E and G remain active,

output data will remain valid for Output Data Hold

time (tAXQX) but will go indeterminate until the next

Address Access.

Figure 7. READ Mode AC Waveforms

Note: WRITE Enable (W) = High.

Table 3. READ Mode AC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

2. CL = 5pF.

Symbol

Parameter(1)

M48T35AY

M48T35AV

Unit

–70

–100

MinMax

tAVAV

READ Cycle Time

100

tAVQV

Address Valid to Output Valid

100

tELQV

Chip Enable Low to Output Valid

100

tGLQV

Output Enable Low to Output Valid

tELQX

(2)

Chip Enable Low to Output Transition

tGLQX

(2)

Output Enable Low to Output Transition

tEHQZ

(2)

Chip Enable High to Output Hi-Z

tGHQZ

(2)

Output Enable High to Output Hi-Z

tAXQX

Address Transition to Output Transition

AI00925

tAVAV

tAVQV

tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A14

DQ0-DQ7

VALID

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