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STW5098BBLT 데이터시트(PDF) 44 Page - STMicroelectronics

부품명 STW5098BBLT
상세설명  Dual low power asynchronous stereo audio Codec with integrated power amplifiers
PDF  85 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STW5098BBLT 데이터시트(HTML) 44 Page - STMicroelectronics

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Control registers
STw5098
44/85
3
ADSPIM
1
0
AD interface in SPI mode sends one channel (left)
AD interface in SPI mode sends two channels (alternated, left first)
0
2-0
ADWL(2:0)
000
001
010
011
100
AD interface word length
16 bit
18 bit
20 bit
24 bit
32 bit
000
Table 22.
CR28 description
Bits
Name
Value
CR28 description
Def.
7AMCKINV
1
0
AMCK is inverted
AMCK is not inverted
0
6DACKP
1
0
DA Bit clock pin (DA_CK) polarity is inverted
DA Bit clock pin (DA_CK) polarity is not inverted
0
5
DASYNCP
1
0
DSP and PCM formats in DA interface
Non delayed format
Delayed format
0
1
0
Delayed, left-aligned, right-aligned and SPI formats in DA interface
DA sync pin (DA_SYNC) polarity is inverted
DA sync pin (DA_SYNC) polarity is not inverted
4DAMONO
1
0
Mono mode: (L+R)/2 from Audio Interface is used on both DAC
channels
Stereo mode
0
3
ADCKP
1
0
AD Bit clock pin (AD_CK) polarity is inverted
AD Bit clock pin (AD_CK) polarity is not inverted
0
2
ADSYNCP
1
0
DSP and PCM formats in AD interface
Non delayed format
Delayed format
0
1
0
Delayed, left-aligned, right-aligned and SPI formats in AD interface
DA sync pin (DA_SYNC) polarity is inverted
DA sync pin (DA_SYNC) polarity is not inverted
1ADMONO
1
0
Mono mode: (L+R)/2 from ADC is sent to both channels in the Audio
interface
Stereo mode
0
0
ADHIZ
1
0
AD data pin (AD_DATA) is in high impedance state when no data is
available
AD data pin (AD_DATA) is forced to 0 when no data is available
0
Table 21.
CR27 description (continued)
Bits
Name
Value
CR27 description
Def.



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