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STR71XF 데이터시트(PDF) 63 Page - STMicroelectronics |
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STR71XF 데이터시트(HTML) 63 Page - STMicroelectronics |
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63 / 77 page ![]() STR71xF Electrical parameters 63/77 BSPI - Buffered Serial Peripheral Interface Subject to general operating conditions for VDD, TA and fPCLK ,unless otherwise specified. Refer to I/O port pin characteristics on page 50 for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Table 36. BSPI characteristics Symbol Parameter Conditions Min Max Unit fSCK 1/tc(SCK) SPI clock frequency Master fPCLK/254 fPCLK/6 5.5 MHz Slave 0 fPCLK/8 3.3 tr(SCK) tf(SCK) SPI clock rise and fall time capacitive charge C=50 pF 14 ns tsu(SS) (1) SS setup time Slave 0 th(SS) (1) SS hold time Slave 0 tw(SCKH) (1) tw(SCKL) (1) SCK high and low time Master fPCLK=33 MHz, presc = 6 73 tsu(MI) (1) tsu(SI) (1) Data input setup time Master Slave 7 0 th(MI) 1)(2) th(SI) 1)(2) Data input hold time Master Slave 1xtPCLK 2xtPCLK th(MI) (1) th(SI) (1) Data input hold time Master fPCLK=33 MHz Slave fPCLK=33 MHz 30 60 ta(SO) 1)(3) Data output access time Slave 0 1.5xtPCLK+42 Slave fPCLK=33 MHz 0 87 tdis(SO) (1)(4) Data output disable time Slave 0 42 tv(SO) (1)(2) Data output valid time Slave (after enable edge) 3xtPCLK+45 fPCLK=33 MHz 135 th(SO) (1) Data output hold time Slave (after enable edge) 0 tv(MO) (1)(2) Data output valid time Master (after enable edge) 2xtPCLK+12 fPCLK=33 MHz 72 th(MO) (1) Data output hold time Master (after enable edge) 0 1. Data based on design simulation and/or characterisation results, not tested in production. 2. Depends on fPCLK. For example, if fPCLK=8MHz, then tPCLK = 1/fPLCLK =125ns and tv(MO) = 255ns. 3. Min. time is the minimum time to drive the output and the max. time is the maximum time to validate the data. 4. Min time is the minimun time to invalidate the output and the max time is the maximum time to put the data in Hi-Z. |
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