MPC8280 datasheet(257/1386 Pages) FREESCALE

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External Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

6-15

MODCK2

AP[2]

TC[1]

BNKSEL[1]

MODCK2—Clock mode input. Defines the operating mode of internal clock circuits.

Address parity 2—(Input/output) The 60x master that drives the address bus, drives also the

address parity signals. The value driven on address parity 2 pin should give odd parity (odd

number of 1s) on the group of signals that includes address parity 2 and A[16–23].

Transfer code 1—The transfer code output pins supply information that can be useful for debug

purposes for each of the MPC8280’s initiated bus transactions.

Bank select 1—The bank select outputs are used for selecting SDRAM bank when the MPC8280

is in 60x-compatible bus mode.

MODCK3

AP[3]

TC[2]

BNKSEL[2]

MODCK3—Clock mode input. Defines the operating mode of internal clock circuits.

Address parity 3—(Input/output) The 60x master that drives the address bus, drives also the

address parity signals. The value driven on address parity 3 pin should give odd parity (odd

number of 1s) on the group of signals that includes address parity 3 and A[24—31].

Transfer code 2—The transfer code output pins supply information that can be useful for debug

purposes for each of the MPC8280’s initiated bus transactions.

Bank select 2—The bank select outputs are used for selecting SDRAM bank when the MPC8280

is in 60x-compatible bus mode. BNKSEL2 is lsb of the three BNKSEL signals.

XFC

External filter capacitance—Input connection for an external capacitor filter for PLL circuitry.

CLKIN1

Clock In—Primary clock input to MPC8280’s PLL. In a PCI system, where the MPC8280 PCI

interface is operated from the PCI bus clock, CLKIN should be connected to the PCI bus clock.

In that case, the 60x bus clock is driven on CLKOUT. See Figure 10-2 and Figure 10-3.

CLKIN2

Clock In2—This is the clock input to the MPC8280’s DLL, which is used for deskewing the output

reference clock. See Figure 10-2 and Figure 10-3.

PCI_MODE

PCI mode pin—This pin enables the PCI bridge of the MPC8280.

• When Low, the PCI bridge is enabled, PCI interface replaces the Local bus.

• When High, the PCI bridge is disabled, the MPC8280 operates with the Local bus.

This pin has an internal pull up resistor so it defaults to Local bus operation.

PA[0–31]

General-purpose I/O port A bits 0–31—CPM port multiplexing is described in Chapter 41,

“Parallel I/O Ports.”

PB[4–31]

General-purpose I/O port B bits 4–31—CPM port multiplexing is described in Chapter 41,

“Parallel I/O Ports.”

PC[0–31]

General-purpose I/O port C bits 0–31—CPM port multiplexing is described in Chapter 41,

“Parallel I/O Ports.”

PD[4–31]

General-purpose I/O port D bits 4–31—CPM port multiplexing is described in Chapter 41,

“Parallel I/O Ports.”

Power Supply

VDD—This is the power supply of the internal logic.

VDDH—This is the power supply of the I/O Buffers.

VCCSYN—This is the power supply of the PLL circuitry.

GNDSYN—This is a special ground of the PLL circuitry.

VCCSYN1—This is the power supply of the core’s PLL circuitry.

Table 6-1. External Signals (continued)

Signal

Description

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