MPC8280 datasheet(260/1386 Pages) FREESCALE

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60x Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

7-2

Freescale Semiconductor

7.1

Signal Configuration

Figure 7-1 shows the 60x bus signal configuration grouping of the MPC8280.

NOTE

The MPC8280 hardware specifications provide a pinout showing numbers

of pins. These are shown in Figure 7-1.

Figure 7-1. Signal Groupings

7.2

Signal Descriptions

This section describes individual MPC8280 60x signals, grouped according to Figure 7-1. Note that the

following sections briefly summarize signal functions. Chapter 8, “The 60x Bus,” describes many of these

signals in greater detail, both in terms of their function and how groups of signals interact.

Bus Request (BR)

Bus Grant (BG)

Address Bus Busy (ABB)

Transfer Start (TS)

Address Parity (AP[0–3])

Transfer Size (TSIZ[0–3])

Transfer Burst (TBST)

Cache Inhibit (CI)

Write-Through (WT)

Address Acknowledge (AACK)

Address Retry (ARTRY)

Data Bus Grant (DBG)

Data Bus Busy (DBB)

Data (D[0–63])

Data Parity (DP[0–7])

Transfer Acknowledge (TA)

Transfer Error Acknowledge (TEA)

Reservation

Data

Processor

Address

Transfer

Attributes

Address

Termination

Transfer Type (TT[0–4])

Global (GBL)

TLBISYNC

Partial Data Valid Indication (PSDVAL)

Transfer Code (TC[0–2])

Address (A[0–31])

Address Parity Error (APE)

State

Termination

Transfer

Arbitration

Start

Bus

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