MPC8280 datasheet(319/1386 Pages) FREESCALE

319 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-11

Figure 9-5. Single Beat Write Example

Figure 9-6 shows an example of a burst write transaction.

Figure 9-6. Burst Write Example

A write transaction is similar to a read transaction except no turnaround cycle is needed following the

address phase because the initiator provides both address and data. Data phases are the same for both read

and write transactions.

9.9.1.3.2

Transaction Termination

The termination of a PCI transaction is orderly and systematic, regardless of the cause of the termination.

All transactions end when FRAME and IRDY are both negated, indicating the idle cycle.

The PCI bridge as an initiator terminates a transaction when FRAME is negated and IRDY is asserted. This

indicates that the final data phase is in progress. The final data transfer occurs when both TRDY and IRDY

are asserted. A master-abort is an abnormal case of an initiated termination. If the PCI bridge detects that

DEVSEL has remained negated for more than four clocks after the assertion of FRAME, it negates

FRAME and then, on the next clock, negates IRDY. On aborted reads, the PCI bridge returns

0xFFFF_FFFF. The data is lost on aborted writes.

ADDR

CMD

PCI_CLK

AD[31:0]

PCI_C/BE[3:0]

FRAME

IRDY

DEVSEL

TRDY

DATA

BYTE ENABLES

ADDR

CMD

PCI_CLK

AD[31:0]

PCI_C/BE[3:0]

FRAME

IRDY

DEVSEL

TRDY

DATA4

DATA1

DATA2

DATA3

BEs 1

BEs 2

BEs 3

BEs 4

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