MPC8280 datasheet(346/1386 Pages) FREESCALE

346 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-38

Freescale Semiconductor

9.11.1.11 Error Control Register (ECR)

The error control register (ECR) register, shown in Figure 9-25, determines whether the IOU asserts an

interrupt or a machine check for the error conditions listed in Table 9-10. The IOU asserts an interrupt or

machine check only if the mask bit for the error condition (refer to Table 9-11) is set. Each bit is defined

as follows:

•

Zero: The IOU issues an interrupt upon the error condition.

•

One: The IOU issues a machine check upon the error condition.

Figure 9-25. Error Control Register (ECR)

PCI_PERR_WR

PCI parity error received on a write. The MPC8280 sinks PERR. This error is only

a function of data.

PCI_PERR_RD

PCI parity error received on a read. The MPC8280 sinks PERR. This error is only

a function of data.

PCI_SERR

PCI SERR received.

PCI_TAR_ABT

PCI target abort

PCI_NO_RSP

PCI no response (no DEVSEL; master abort).

PCI_DATA_PAR_RD

PCI read data parity error. The MPC8280 sources PERR. This error is only a

function of data.

PCI_DATA_PAR_WR

PCI write data parity error. The MPC8280 sources PERR. This error is only a

function of data.

PCI_ADDR_PAR

PCI address parity error (read or write).

Field

—

Reset

0000_0000_0000_0000

R/W

Addr

0x1088E

Field

—

I2O_

DBMC

NMI

IRA

I2O_

IPQO

I2O_

OFQO

PERR_

SERR

TAR_

ABT

NO_

RSP

DATA_

PAR_

DATA_

PAR_

ADDR_

PAR

Reset

0000_0000_1111_1111

R/W

Addr

0x1088C

Table 9-11. EMR Field Descriptions (continued)

Bits

Name

Description

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