MPC8280 datasheet(347/1386 Pages) FREESCALE

347 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-39

Table 9-12 describes ECR fields.

9.11.1.12 PCI Error Address Capture Register (PCI_EACR)

The PCI error address capture register (PCI_EACR), shown in Figure 9-26, stores the address associated

with the first PCI error captured.

Figure 9-26. PCI Error Address Capture Register (PCI_EACR)

Table 9-12. ECR Field Descriptions

Bits

Name

Description

31–13

—

Reserved, should be cleared

I2O_DBMC

I2O doorbell machine check

ESR[I2O_DBMC] causes an interrupt.

1 ESR[I2O_DBMC] (if enabled) causes a machine check.

NMI

General error/interrupt indication

IRA

Illegal register access with incorrect size

I2O_IPQO

I2O inbound post queue overflow

I2O_OFQO

I2O outbound free queue overflow

PCI_PERR_WR

PCI parity error received on a write

PCI_PERR_RD

PCI parity error received on a read

PCI_SERR

PCI SERR received

PCI_TAR_ABT

PCI target abort

PCI_NO_RSP

PCI no response (no DEVSEL; master abort)

PCI_DATA_PAR_RD

PCI read data parity error

PCI_DATA_PAR_WR

PCI write data parity error

PCI_ADDR_PAR

PCI address parity error (read or write)

Field

PCI_EAR

Reset

0000_0000_0000_0000

R/W

Addr

0x10892

Field

PCI_EAR

Reset

0000_0000_0000_0000

R/W

Addr

0x10890

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