MPC8280 datasheet(354/1386 Pages) FREESCALE

354 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-46

Freescale Semiconductor

Figure 9-32. PCI Bridge PCI Configuration Registers

The PCI configuration registers are accessible from the core through an indirect method discussed in

“Section 9.11.2.26, PCI Configuration Register Access from the Core” on page 62. The registers are

accessible from the PCI bus through the PCI configuration transaction when the PCI bridge is in agent

mode.

The following sections describe the individual PCI configuration registers.

MIN GNT

0x00

9.11.2.20/9-58

MAX LAT

0x00

9.11.2.21/9-58

Reserved

—

PCI function

R/W

0x0000

9.11.2.22/9-59

PCI arbiter control register

R/W

Mode-dependent

9.11.2.23/9-60

Hot swap register block

R/W

0x00nn_0006

9.11.2.24/9-61

9.11.2.25/9-61

Address offset

(Hex)

Device ID (0x18C0)

Vendor ID (0x1057)

PCI status

PCI command

Class code

Subclass code

Standard programming

Revision ID

BIST control

Header type

Latency timer

Cache line size

PIMMR base address register

GPLA base address register 0

GPLA base address register 1

••

—

•

Subsystem ID

Subsystem vendor ID

••

—

••

—

Capabilities pointer

—

MAX LAT

MIN GNT

Interrupt pin

Interrupt line

—

PCI arbiter control

PCI function

Hot swap CSR

Hot swap capability ID

Table 9-19. PCI Bridge PCI Configuration Registers (continued)

Address

(offset)

Access

Reset

Section/Page

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