MPC8280 datasheet(388/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-80

Freescale Semiconductor

9.12.3.4.3

Outbound Message Interrupt Status Register (OMISR)

OMISR contains the interrupt status of the I2O, door bell, and outbound message registers. A PCI device

acknowledges the outbound message interrupt by writing a 1 to the appropriate status bit: OMISR[OM1I]

or OMISR[OM0I]. This clears both the interrupt and the corresponding status bit. The local processor

provokes an outbound message interrupt by writing to either of the two outbound message registers:

OMR0 or OMR1. OMISR should be accessed only from the PCI bus IFQPR should be accessed only from

the PCI bus.

Figure 9-75. Outbound Message Interrupt Status Register (OMISR)

Table 9-60 describes OMISR fields.

Table 9-59. OFQPR Field Descriptions

Bits

Name

Description

31–0

OFQP

Outbound FIFO queue port. Reading this register will return the MFA from outbound

post list FIFO. Writing this register will post the MFA to the outbound free list FIFO.

Field

—

Reset

0000_0000_0000_0000

R/W

Refer to Table 9-60.

Addr

0x10432

Field

—

OPQI

—

ODI

—

OM1I OM0I

Reset

0000_0000_0000_0000

R/W

Refer to Table 9-60.

Addr

0x10430

Table 9-60. OMISR Field Descriptions

Bits

Name

R/W

Description

31–6

—

Reserved, should be cleared.

OPQI

Outbound post queue interrupt. When set indicates that a message or messages

are posted in the outbound queue. To clear the interrupt, software has to read all

MFAs in the outbound post FIFO. This bit is set regardless of the state of the

OPQIM mask bit.1

—

Reserved, should be cleared.

ODI

Outbound doorbell interrupt. When set indicates that there is an outbound doorbell

interrupt.

—

Reserved, should be cleared.

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