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MPC8280 데이터시트(PDF) 558 Page - Freescale Semiconductor, Inc |
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MPC8280 데이터시트(HTML) 558 Page - Freescale Semiconductor, Inc |
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558 / 1386 page ![]() Communications Processor Module Overview MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 14-8 Freescale Semiconductor 14.3.6 Execution from RAM The CP has an option to execute microcode from a portion of user RAM located in the dual-port RAM. In this mode, the CP fetches instructions from both the dual-port RAM and its own private ROM. This mode allows Freescale to add new protocols or enhancements to the MPC8280 in the form of RAM microcode packages. If preferred, the user can obtain binary microcode from Freescale and load it into the dual-port RAM. 14 FCC2 receive 15 FCC2 transmit 16 FCC3 receive 17 FCC3 transmit 18 SCC1 receive 19 SCC1 transmit 20 SCC2 receive 21 SCC2 transmit 22 SCC3 receive 23 SCC3 transmit 24 SCC4 receive 25 SCC4 transmit 26 IDMA[1–4] emulation (option 2)1 27 SMC1 receive 28 SMC1 transmit 29 SMC2 receive 30 SMC2 transmit 31 SPI receive 32 SPI transmit 33 I 2C receive 34 I 2C transmit 35 RISC timer table 36 IDMA[1–4] emulation (option 3)1 1 The priority of each IDMA channel is programmed independently. See the RCCR[DR xQP] description in Section 14.3.7, “RISC Controller Configuration Register (RCCR).” 2 Not on MPC8270 and MPC8275 Table 14-2. Peripheral Prioritization (continued) Priority Request |
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