MPC8280 datasheet(562/1386 Pages) FREESCALE

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Communications Processor Module Overview

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

14-12

Freescale Semiconductor

the miscellaneous parameter RAM portion of the CPM's internal dual-port Ram (DPR). The user can then

access this location in DPR to determine which version of CPM microcode is contained in that device.

Table 14-5 describes which microcode version numbers are associated with each silicon revision.

14.4

Command Set

The core issues commands to the CP by writing to the CP command register (CPCR). The CPCR rarely

needs to be accessed. For example, to terminate the transmission of an SCC’s frame without waiting until

the end, a STOP TX command must be issued through the CP command register (CPCR).

14.4.1

CP Command Register (CPCR)

The core should set CPCR[FLG], shown in Figure 14-6, when it issues a command and the CP clears FLG

after completing the command, thus indicating to the core that it is ready for the next command.

Subsequent commands to the CPCR can be given only after FLG is clear. However, the software reset

command issued by setting RST does not depend on the state of FLG, but the core should still set FLG

when setting RST.

Table 14-5. RISC Microcode Revision Number

Address

Name

Width

Description

RAM Base + 0x8AF0

REV_NUM

Hword

Microcode revision number. If working with newer silicon than what is

shown below, consult the product page on the web.

Rev 0.0—0x0070

Rev 0.1—0x0070

RAM Base + 0x8AF2

—

Hword

Reserved

Field RST

PAGE

Sub-block code (SBC)

—

FLG

Reset

0000_0000_0000_0000

R/W

Addr

0x119C0

Field

—

MCN

EP1

OPCODE

Reset

0000_0000_0000_0000

R/W

Addr

0x119C2

1 Only in USB. Otherwise reserved.

Figure 14-6. CP Command Register (CPCR)

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