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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MPC8280 데이터시트(PDF) 601 Page - Freescale Semiconductor, Inc |
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MPC8280 데이터시트(HTML) 601 Page - Freescale Semiconductor, Inc |
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601 / 1386 page  Serial Interface with Time-Slot Assigner MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 15-23 Figure 15-17 shows the effects of changing FE when CE = 0 with no frame sync delay. Figure 15-17. Falling Edge (FE) Effect When CE = 0 and xFSD = 00 L1TXD L1ST L1SYNC L1CLK (Bit-0) (On Bit-0) xFSD=00 (FE=1) CE=0 The L1ST is Driven from Sync. Data is Driven From Clock High. L1TXD L1ST L1SYNC (Bit-0) (On Bit-0) (FE=1) L1ST is Driven from Clock Low. L1TXD L1ST L1SYNC (Bit-0) (On Bit-0) (FE=0) Both the Data and L1ST from Sync when Asserted during Clock High. Rx Sampled Here L1TXD L1ST L1SYNC (Bit-0) (On Bit-0) (FE=0) Both the Data and L1ST from the Clock when Asserted during Clock Low. |
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