MPC8280 datasheet(685/1386 Pages) FREESCALE

685 / 1386 page

Serial Communications Controllers (SCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

20-5

Figure 20-3 shows GSMR_L.

Table 20-2 describes GSMR_L fields.

28–29

SYNL

Sync length (BISYNC and transparent mode only). See the data synchronization register (DSR)

definition in Section 23.9, “Sending and Receiving the Synchronization Sequence,” (BISYNC) and

Section 24.4.1.1, “In-Line Synchronization Pattern,” (transparent).

00 An external sync (CD) is used instead of the sync pattern in the DSR.

01 4-bit sync. The receiver synchronizes on a 4-bit sync pattern stored in the DSR. This sync and

additional syncs can be stripped by programming the SCC’s parameter RAM for character

recognition.

10 8-bit sync. Should be chosen along with the BISYNC protocol to implement mono-sync. The

receiver synchronizes on an 8-bit sync pattern in the DSR.

11 16-bit sync. Also called BISYNC. The receiver synchronizes on a 16-bit sync pattern stored in

the DSR.

RTSM

RTS mode. Determines whether flags or idles are to be sent. Can be changed on-the-fly.

0 Send idles between frames as defined by the protocol and the TEND bit. RTS is negated between

frames (default).

1 Send flags/syncs between frames according to the protocol. RTS is always asserted whenever

the SCC is enabled.

RSYN

Receive synchronization timing (totally transparent mode only).

0 Normal operation.

1 If CDS = 1

, CD should be asserted on the second bit of the Rx frame rather than on the first.

012

3456

Field

—

EDGE

TCI

TSNC

RINV TINV

TPL

TPP

TEND

TDCR

Reset

0000_0000_0000_0000

R/W

Addr

0x11A00 (SCC1); 0x11A20 (SCC2); 0x11A40 (SCC3); 0x11A60 (SCC4)

Field

RDCR

RENC

TENC

DIAG

ENR ENT

MODE

Reset

0000_0000_0000_0000

R/W

Addr

0x11A02 (SCC1); 0x11A22 (SCC2); 0x11A42 (SCC3); 0x11A62 (SCC4)

Figure 20-3. GSMR_L—General SCC Mode Register (Low Order)

Table 20-2. GSMR_L Field Descriptions

Bit

Name

Description

—

Reserved, should be cleared.

Table 20-1. GSMR_H Field Descriptions (continued)

Bit

Name

Description

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