MPC8280 datasheet(717/1386 Pages) FREESCALE

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SCC UART Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

21-11

21.14 Fractional Stop Bits (Transmitter)

The asynchronous UART transmitter, shown in Figure 21-5, can be programmed to send fractional stop

bits. The FSB field in the data synchronization register (DSR) determines the fractional length of the last

stop bit to be sent. FSB can be modified at any time. If two stop bits are sent, only the second is affected.

Idle characters are always sent as full-length characters

Table 21-6 describes DSR fields.

Field

—

FSB

——

—

Reset

1111

R/W

Addr

Figure 21-5. Asynchronous UART Transmitter

Table 21-6. DSR Fields Descriptions

Bit

Name

Description

—

0b0

1–4

FSB

Fractional stop bits. For 16

× oversampling:

1111 Last transmitted stop bit 16/16. Default value after reset.

1110 Last transmitted stop bit 15/16.

…

1000 Last transmitted stop bit 9/16.

0xxx Invalid. Do not use.

For 32

× oversampling:

1111 Last transmitted stop bit 32/32. Default value after reset.

1110 Last transmitted stop bit 31/32.

…

0000 Last transmitted stop bit 17/32.

For 8

× oversampling:

1111 Last transmitted stop bit 8/8. Default value after reset.

1110 Last transmitted stop bit 7/8.

1101 Last transmitted stop bit 6/8.

1100 Last transmitted stop bit 5/8.

10xx Invalid. Do not use.

0xxx Invalid. Do not use.

The UART receiver can always receive fractional stop bits. The next character’s start bit can begin

any time after the three middle samples have been taken.

5–6

—

0b11

7–8

—

0b00

9–14

—

0b111111

—

0b0

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