MPC8280 datasheet(1134/1386 Pages) FREESCALE

1134 / 1386 page

ATM AAL2

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

33-28

Freescale Semiconductor

33.4.4.5

CPS Switch Rx Queue Descriptor

The switch RxQD, shown in Figure 33-18, is used for CIDs that are being switched from one

PHY1 |VP1 |VC1 |CID1 to another PHY2 |VP2 |VC2 |CID2. The RxQD contains the pointer to the

TxQD that controls the TxBD table through which the packet is transferred.

The switch RxQD also contains the translation CID that is saved with the packet in the transmit buffer. A

PPD mode enables the discarding of the rest of an SSSAR frame when a buffer is not available.

Note that the CPS switch RxQD must be unique for every Rx switched CID.

Table 33-8. CPS RxBD Field Descriptions

Offset

Bits

Name1

Boldfaced entries must be initialized by the user.

Description

0x00

Buffer empty bit

0 The CPS RX buffer is full or data reception was aborted due to an error. The core

can read or write any fields of this RxBD. The CP does not use this BD while E

remains zero.

1 The CPS RX buffer is empty or reception is in progress. This is controlled by the CP.

Once E is set, the core should not access any fields of this buffer.

Continuous mode

0 Normal operation

1 The CP does not clear E after this BD is closed, allowing the associated buffer to

be reused automatically when the CP next accesses this BD. However, the E bit is

cleared if an error occurs while receiving, regardless of the CM bit setting.

Wrap (final BD in table)

0 This is not the last BD in the RxBD table.

1 This is the last BD in the RxBD table of this current channel. After this buffer has

been used, the CP receives incoming data for this channel into the first BD in the

table. The number of RxBDs in this table is programmable and is determined only

by the W bit. The current table cannot exceed 64 Kbytes.

Interrupt

0 The CP will not issue an interrupt after this buffer is serviced.

1 The CP will issue an interrupt after this buffer is serviced if the RBM bit in the RxQD

is set.

4–6

—

Reserved, should be cleared during initialization.

Uncompleted packet

0 No error occurred in this packet

1 A receive error occurred that caused this packet to be uncompleted. The receive

error type is reported to the interrupt queue.

8–15

CPS Packet

Header

Contains the beginning of the packet header. See Figure 33-10 for the CPS packet

header format.

0x02

—

CPS Packet

Header

Contains the rest of the packet header. The CP checks the packet HEC and if

appropriate, indicates a packet HEC error in an interrupt queue entry with CID = 0.

See Figure 33-10 for the CPS packet header format.

0x04

—

RXDBPTR

Rx data buffer pointer. Points to the address of the associated buffer. There are no

byte-alignment requirements for the buffer, and it may reside in either internal or

external memory. This value is not modified by the CP.

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