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MPC8280 데이터시트(PDF) 1181 Page - Freescale Semiconductor, Inc

부품명 MPC8280
상세설명  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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Inverse Multiplexing for ATM (IMA)
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
34-35
Table 34-12 describes the IGRSTATE bit fields.
34.4.4.2.3
IMA Receive Group Frame Size
The fields of the IRGFS register are shown in Figure 34-19.
Table 34-13 describes the IRGFS bit fields.
34.4.4.2.4
Receive Group Order Tables
The receive group order tables define the order of the links in the round-robin extraction of cells to the
links of the IMA group. The table consists of an array of bytes ordered from first link to last link, with each
byte providing the PHY address of its associated link. The end of the table is indicated by an entry
programmed to 0x1F.
Two group order tables are used in order to allow for on-the-fly changes (i.e. to add or remove links), while
making certain that the changes only occur at the end of a round-robin cycle. IGRCNTL[GOTP] indicates
which group order table pointer (and therefore, group table) is currently in use. Changes should be made
Table 34-12. IGRSTATE Field Descriptions
Bits
Name
Description
0
IDCR_DN
IDCR Done. Microcode-managed parameter. When this bit is set by the microcode, the TRLR
value is valid and can be used to program the IDCR timer entry values for this group. Initialize
to zero at group startup.
1–2
GDSS
Group delay synchronization state. Initialize to zero at group startup. Must be changed by
software to 01 after sufficient links have achieved frame synchronization. Subsequently
managed by microcode.
00 Group delay synchronization process inhibited.
01 Group delay synchronization process enabled.
10 Group delay synchronization process in progress.
11 Group delay synchronized.
Refer to Section 34.5.4.10, “Receive Event Response Procedures".
3–7
—
Reserved, initialize to zero.
01
67
Field
0
—
GSC-M
Figure 34-19. IMA Receive Group Frame Size (IGRSTATE)
Table 34-13. IRGFS Field Descriptions
Bits
Name
Description
0
0
Reserved, initialize to zero.
1–5
—
Reserved, initialize to zero.
6–7
GSC-M
IMA Receive Group Frame Size
Bits 0-5: Reserved
Bits 6-7 - GSC_M: Value of received ICP cell Group Status Contl field
(Bits 1:0) which determine the IMA frame size. This field must be
programmed before links in the group are assigned



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