MPC8280 datasheet(1185/1386 Pages) FREESCALE

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Inverse Multiplexing for ATM (IMA)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

34-39

34.4.5.1.3

IMA Transmit Interrupt Status (ITINTSTAT)

The fields of the ITINTSTAT register are shown in Figure 34-23.

Table 34-18 describes the ITINTSTAT bit fields.

LGSU

Link/group startup flag. Microcode-managed parameter. Will be set by the microcode after the

link’s transmit queue has reached target average depth of 3 cells. While this bit is cleared, the

link will transmit only filler cells. Initialize to zero at link startup.

TQSU

Transmit queue startup flag. Microcode-managed parameter. Will be set by the microcode after

the first cell has been sent to the transmit queue. Initialize to zero at link startup.

LDC

Link Due Cell - Link is due cell from round robin distribution. Microcode managed parameter

initialize to 0. Used for optional TRL Service Latency enhancement only.

6–7

—

Reserved, initialize to zero.

34567

Field

—

PTQO

TQO

PTQU

TQU

Figure 34-23. IMA Transmit Interrupt Status (ITINTSTAT)

Table 34-18. ITINTSTAT Field Descriptions

Bits

Name

Description

0–3

—

Reserved, initialize to zero.

PTQO

Persistent transmit queue overflow. Set when a transmit queue overflow occurs for two cells in

a row. Further transmit queue overflow events are masked when this bit is set, in order to avoid

a ’flood’ of interrupts. This bit can be used to distinguish a temporary overflow condition (which

could be caused by a rate differential between the TRL and non-TRL link which was out of

compensatable range), or a persistent overflow condition (which could be caused by a more

permanent condition, such as a failure of this link’s PHY device).

Initialize to zero at link startup.

TQO

Transmit queue overflow. Set when a transmit queue overflow occurs; cleared when a cell is

successfully transmitted. As this bit is set or cleared on a cell-by-cell basis, it may no longer be

set when software reads it if the overflow condition was only temporary. PTQO should be used

instead to distinguish between persistent or temporary underrun conditions.

PTQU

Persistent transmit queue underrun. Set when a transmit queue underrun occurs for two cells

in a row. Further transmit queue underrun events are masked when this bit is set, in order to

avoid a ’flood’ of interrupts. This bit can be used to distinguish a temporary underrun condition

(which could be caused by a rate differential between the TRL and non-TRL link which was out

of compensatable range), or a persistent underrun condition (which could be caused by a more

permanent condition, such as a TRL failure).

Initialize to zero at link startup.

TQU

Transmit queue underrun. Set when a transmit queue underrun occurs; cleared when a cell is

successfully transmitted. As this bit is set or cleared on a cell-by-cell basis, it may no longer be

set when software reads it if the underrun condition was only temporary. PTQU should be used

instead to distinguish between persistent or temporary underrun conditions.

Initialize to zero at link startup.

Table 34-17. ILTSTATE Field Descriptions (continued)

Bits

Name

Description

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