MPC8280 datasheet(1233/1386 Pages) FREESCALE

1233 / 1386 page

ATM Transmission Convergence Layer

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

35-17

Step 5

The TCx layer block should be configured using the TCMODEx and CDSMR1 registers as shown in

Table 17. Note that the TC layer must be enabled after both FCC2 and CPM MUX have been programmed.

Step 6

Program the SI to retrieve the data bits (192 bits) out of the T1 frame (193 bits). The SI frame pattern is

programmed in the SI RAM (Rx or Tx), as shown in Table 18.

Step 7

The last step in this example is to initialize the serial interface registers and enable TDM—in this case

TDMa on SI1 as shown in Table 19.

Table 35-10. Programming the TC Layer Block

Init Values

Description

TCMODE1 = 0xC202

Enable TC Layer Rx and Tx, no error correction on header, the TC is the only PHY on

UTOPIA

CDSMR1 = 0x3980

ALPHA = 7, DELTA = 6 (default values)

Table 35-11. Programming the SI RAM (Rx or Tx) for a T1 Application

Init Values

Description

SI_RAM[00]=0x0000

1 bit is ignored.

SI_RAM[02]=0x015E

Route 8 bytes to FCC2.

SI_RAM[04]=0x015E

Route 8 bytes to FCC2.

SI_RAM[06]=0x015F

Route 8 bytes to FCC2 and go back to the first entry in table.

Table 35-12. Programming SI Registers to Enable TDM

Init Values

Description

SI1AMR = 0x0040

Common Receive and Transmit Pins for TDMa

SI1GMR = 01

Enable TDMa

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