MPC8280 datasheet(1236/1386 Pages) FREESCALE

1236 / 1386 page

Fast Ethernet Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

36-2

Freescale Semiconductor

10-Mbps Ethernet basic timing specifications follow:

•

Transmits at 0.8 µs per byte

•

The preamble plus start frame delimiter is sent in 6.4 µs.

•

The minimum interframe gap is 9.6 µs.

•

The slot time is 51.2 µs.

100-Mbps Ethernet basic timing specifications follow:

•

Transmits at 0.08 µs per byte

•

The preamble plus start frame delimiter is sent in 0.64 µs.

•

The minimum interframe gap is 0.96 µs.

•

The slot time is 5.12 µs.

36.1

Fast Ethernet on the MPC8280

When a general FCC mode register (GFMRx[MODE]) selects Ethernet protocol, that FCC performs the

full set of IEEE 802.3/Ethernet CSMA/CD media access control (MAC) and channel interface functions.

Figure 36-2 shows a block diagram of the FCC Ethernet control logic.

Figure 36-2. Ethernet Block Diagram

36.2

Features

The following is a list of Fast Ethernet key features:

•

Support for Fast Ethernet through the MII (media-independent interface)

•

Performs MAC (media access control) layer functions of Fast Ethernet and IEEE 802.3x

Shifter

Receive

Receiver

Control

UNIT

FIFO

Shifter

Transmit

Transmitter

Control

Unit

FIFO

Slot Time

Clock

Generator

Internal Clocks

Control

Registers

TXD[3–0]

RXD[3–0]

Peripheral Bus

60x-Bus

Data

RX_CLK

TX_CLK

And Defer

Counter

TX_ER

CRS

COL

RX_ER

TX_EN

COL

RX_DV

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