MPC8280 datasheet(1255/1386 Pages) FREESCALE

1255 / 1386 page

Fast Ethernet Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

36-21

36.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM)

The FCCE, shown in Figure 36-7, is used as the Ethernet event register when the FCC functions as an

Ethernet controller. It generates interrupts and reports events recognized by the Ethernet channel. On

recognition of an event, the Ethernet controller sets the corresponding FCCE bit. Interrupts generated by

this register can be masked in the Ethernet mask register (FCCM).

The FCCM has the same bit format as FCCE. Setting an FCCM bit enables and clearing a bit masks the

corresponding interrupt in the FCCE.

The FCCE can be read at any time. Bits are cleared by writing ones; writing zeros does not affect bit values.

Unmasked FCCE bits must be cleared before the CP clears the internal interrupt request.

7–8

—

Reserved, should be zero

PRO

Promiscuous

0 Check the destination address of incoming frames.

1 Receive the frame regardless of its address. A CAM can be used for address filtering when

FSMR[CAM] is set.

FCE

Flow control enable

0 Flow control is not enabled

1 Flow control is enabled

RSH

Receive short frames

0 Discard short frames (frames smaller than the value specified in MINFLR).

1 Receive short frames.

12–13

—

Reserved, should be zero.

RMII

RMII interface mode

0 MII interface

1 RMII interface. RMII to/from MII conversion logic is enabled.

15–20

—

Reserved, should be zero.

CAM

CAM address matching

0 Normal operation.

1 Use the CAM for address matching; CAM result (16 bits) is added at the end of the frame.

BRO

Broadcast address

0 Receive all frames containing the broadcast address.

1 Reject all frames containing the broadcast address unless FSMR[PRO] = 1.

—

Reserved, should be zero

24–25

CRC

CRC selection

0x Reserved.

10 32-bit CCITT-CRC (Ethernet). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 +

X5 + X4 + X2 + X1 +1. Select this to comply with Ethernet specifications.

11 Reserved.

26–31

—

Reserved, should be zero

Table 36-8. FPSMR Ethernet Field Descriptions (continued)

Bits

Name

Description

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