MPC8280 datasheet(1256/1386 Pages) FREESCALE

1256 / 1386 page

Fast Ethernet Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

36-22

Freescale Semiconductor

Table 36-9 describes FCCE/FCCM fields.

Figure 36-7. Ethernet Event Register (FCCE)/Mask Register (FCCM)

Field

—

GRA RXC

TXC

TXE

RXF

BSY

TXB

RXB

Reset

0000_0000_0000_0000

R/W

Addr

0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/

0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3)

Field

—

Reset

0000_0000_0000_0000

R/W

Addr

0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/

0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3)

Table 36-9. FCCE/FCCM Field Descriptions

Bits

Name

Description

0–7

—

Reserved, should be cleared.

GRA

Graceful stop complete. A graceful stop, initiated by the GRACEFUL STOP TRANSMIT command, is

complete. When the command is issued, GRA is set as soon the transmitter finishes sending a

frame in progress. If no frame is in progress, GRA is set immediately.

RXC

RX control. A control frame has been received (FSMR[FCE] must be set). As soon as the transmitter

finishes sending the current frame, a pause operation is performed.

TXC

TX control. An out-of-sequence frame was sent.

TXE

Tx error. An error occurred on the transmitter channel. This event is not maskable via the TxBD[I] bit

RXF

Rx frame. Set when a complete frame is received on the Ethernet channel. This event is not

maskable via the RxBD[I] bit.

BSY

Busy condition. Set when a frame is received and discarded due to a lack of buffers.

TXB

Tx buffer. Set when a buffer has been sent on the Ethernet channel.

RXB

Rx buffer. A buffer that was not a complete frame is received on the Ethernet channel.

16–31

—

Reserved, should be cleared.

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