MPC8280 datasheet(1278/1386 Pages) FREESCALE

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FCC HDLC Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

37-16

Freescale Semiconductor

Figure 37-8. HDLC Interrupt Event Example

37.10 FCC Status Register (FCCS)

The FCCS register, shown in Figure 37-9, allows the user to monitor real-time status conditions on the

RXD line. The real-time status of the CTS and CD signals are part of the parallel I/O port; see Chapter 41,

“Parallel I/O Ports.”

01234567

Field

—

Reset

0000_0000

R/W

Addr

0x11318 (FCCS1), 0x11338 (FCCS2), 0x11358 (FCCS3)

Figure 37-9. FCC Status Register (FCCS)

IDL

FLG

RXB

RXF

IDL

Line Idle

Stored in Rx Buffer

RXD

Frame

Received by HDLC

Time

Line Idle

TXD

RTS

Frame

Transmitted by HDLC

CTS

TXB

Line Idle

Stored in Tx Buffer

Notes:

HDLC FCCE

Events

1. RXB event assumes receive buffers are 6 bytes each.

2. The second IDL event occurs after 15 ones are received in a row.

3. The FLG interrupts show the beginning and end of flag reception.

4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency.

5. The CD event must be programmed in the parallel I/O port, not in the FCC itself.

Notes:

HDLC FCCE

Events

1. TXB event shown assumes all three bytes were put into a single buffer.

2. Example shows one additional opening flag. This is programmable.

AAC

I CR CR F

FLG

6. F = flag, A = address byte, C = control byte, I = information byte, and CR = CRC byte

C CR CR F

3. The CT event must be programmed in the parallel I/O port, not in the FCC itself.

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